In complementary metal oxide semiconductor (CMOS) devices it is well known that insulated gate field effect transistor (IGFET) devices transconductance falls off with increasing temperature. It is also known that IGFET transconductance is proportional to the square root of current. Therefore, if these transistors are provided with a bias current that is suitably proportional to absolute temperature (PTAT), the transconductance change with temperature can be substantially reduced. A conventional IC PTAT current will have a temperature coefficient of about 3300 parts per million (ppm) per degree Kelvin minus the positive temperature coefficient of the integrated resistor used.
Should a richly doped diffused resistor be utilized, the net temperature coefficient could be about +3000 ppm per degree Kelvin. Alternatively, a lightly doped resistor can be employed to deliberately create a temperature coefficient of about zero, which may be very desirable in certain cases.
In conventional CMOS construction two forms are commonly found. These are P well and N well construction. In P well construction the substrate is an N type semiconductor. P wells, which are to contain N channel transistors, are formed in the substrate. Thus, any N channel transistor fabricated in a P well will have its back gate electrode connected to the well. P channel transistors are fabricated directly into the N type substrate so that their back gates are all substrate dedicated.
If a heavily doped N type region is formed in a P well, for example an IGFET source or drain, the resulting PN junction, when forward biased, can inject minority current carriers into adjacent portions of the P well. These carriers can diffuse across the well and be collected at the substrate. Thus, an NPN bipolar junction transistor (BJT) is present with its collector dedicated to the substrate. While this device is normally regarded as parasitic it can be used in common collector circuit functions.
In N well construction the substrate is a P type semiconductor with N wells formed therein. P channel IGFETs are formed in the P wells while N channel IGFETs are formed directly in the substrate. In this form of construction the N wells can become the base of a PNP BJT which has its collector dedicated to the substrate.
A copending patent application Ser. No. 304,701, now abandoned, was filed Sept. 22, 1981, by Thomas M. Frederiksen et al. It is titled A LATERAL TRANSISTOR USEFUL IN CMOS INTEGRATED CIRCUITS and is assigned to the assignee of the present invention. In this applicaton the combination of a lateral collector with the conventional parasitic BJT creates a structure in which a non-dedicated collector is available for circuit applications. Actually, the device is a dual collector BJT in which only one collector is dedicated or connected to the circuit substrate. The teaching in this application is incorporated herein by reference.